1. Field of the Invention
This invention relates generally to integrated circuit delay lines, and more particularly to the test, characterization, and calibration of delay lines in microprocessors and digital signal processors.
2. Background of the Invention
Programmable digital delay lines, delay lines fabricated from N equal delay elements, are important components in microprocessor and digital signal processor devices. Examples of the applications of these devices include: providing accurate delay signals edges for the purpose of correcting/adjusting signal skews; accurately adjusting the width of a pulse to a finer resolution than is possible with the device system clock (especially pulse width modulation {PWM}); and generating frequencies at finer resolution steps using a ring oscillator technique than is possible with a system clock.
Referring to FIG. 1, a typical controllable digital delay line is illustrated. The delay line is a plurality of series coupled delay elements d0 through dN-1. Coupled to the output terminal of each delay element dn is the input terminal of gate gn. A multiplexer 11 activates gate gn in response to a numerical value n. In this manner, in response, to an input value of n, the gate gn is activated. Thereafter, a pulse applied to the DELAY IN terminal of the delay element d0 will be transmitted to the output terminal of gate gn. The input pulse is therefore delayed by gates d0 through dn, and is applied to the DELAY OUT terminal.
Because geometry determines the characteristics of the delay elements, each delay element can be designed to match the other delay elements. However, this matching only insures relative delay element accuracy. More importantly, a “measure” of the absolute delay for each delay element is needed to have a useful value in an application. This absolute value needs to be dynamically determined over temperature and process variations. The embedded delay structure operates within a clocked system (i.e., necessary for microprocessor devices or digital signal processor deices), the clocked system usually based on a quartz crystal. If a determination can be made as to how many delay elements give a delay equal to the system clock period, Tsys, of the system, then important calibration information needed to program the delay structure with absolute times is provided.
Referring to FIG. 2, an example how m delay elements are needed to span a 100 nS system clock is shown. (Note the assumption is that the delay structure is designed with a sufficiently large number of delay elements to span the width of the system clock under both temperature and process variations.) When m is known, absolute time delay values ranging from 0-Tsys can be programmed according to the following relationship:Dabs(i)=Tsys*i/m 
Although the advantages of using delay lines are well-known, problems have been found when delay lines are embedded in integrated circuits. Two important areas that should be addressed to derive the full benefit of the embedded delay lines are 1.) the test and characterization during the manufacturing process, and 2.) the delay line calibration in the field.
With respect to the testing and the characterization during the manufacturing process, the delay structures are embedded in microprocessor and digital signal processor devices and, consequently, share the same process technology, i.e., high density complementary metal oxide semiconductor (CMOS) technology. Delay values for each device can be on the order of 100 ps. Even expensive and sophisticated chip testers can have problem resolving the timing resolution required to test and characterize such delay elements. Moreover, accessing such elements via device pins introduces large amounts of input/output (I/O) pad delays, thereby skewing the actual measurement itself.
With respect to the field calibration, although each delay element can be made equal to the other delay elements, (achieved by equal geometry), process and temperature variations prevent identical absolute delay values. For the delay structures to be useful in an application, the dynamic determination of the absolute value of the delays is necessary for use in a background calibration scheme.
A need has therefore been felt for apparatus and an associated method having the feature of improved determination of the delay line characteristics. It is another feature of the apparatus and associated method provide a stand-alone test and characterization of a delay line in an integrated circuit. It would be a further feature of the apparatus and associated method to provide test and characterization techniques involve frequency and period-based techniques. It would be a still further feature of the apparatus and associated method to permit data relevant to the test and characterization of a delay line to be analyzed either with an associated processing unit or external testing equipment. It is still a further feature of the apparatus and associated method to provide an iterative calibration method based on counters averaged over time. It would be a more particular feature of the apparatus and associated method to provide an iterative calibration technique that is tolerant to noise and to meta-stability. It is still another feature of the apparatus and associated method to provide a characterization scheme that can run concurrently with an application program.